1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a stacked semiconductor package which has a structure suitable for improving the manufacturing yield and a method for manufacturing the same.
2. Description of the Related Art
In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demand toward miniaturization and mounting reliability. Recently, as miniaturization and high performance are demanded in electric and electronic appliances, various stacking techniques have been developed.
The term “stack” that is referred to in the semiconductor industry means to vertically pile at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using a stacking technology, it is possible to realize a product having memory capacity at least two times greater than that obtainable through semiconductor integration processes. Since stacked semiconductor packages have advantages in terms of not only memory capacity but also mounting density and mounting area utilization efficiency, research and development for stacked semiconductor packages have been accelerated.
As an example of a stacked semiconductor package, a structure has been proposed, in which through electrodes are formed in semiconductor chips so that upper and lower semiconductor chips are physically and electrically connected with one another by the through electrodes. The manufacturing procedure of such stacked semiconductor package using through electrodes is as follows.
Holes are defined at desired positions of respective semiconductor chips through an etching process at a wafer level, and through electrodes are formed in the holes using a metallic substance through a plating process. Thereafter, with a carrier substrate attached to the front surface of a wafer, the through electrodes are exposed by back-grinding the back surface of the wafer. After detaching the carrier substrate, the semiconductor chips of the wafer are individualized by sawing the wafer. Then, by stacking at least two of the individualized semiconductor chips on a substrate having circuit patterns by using the through electrodes, a stacked semiconductor package is formed.
In the stacked semiconductor package using through electrodes, since electrical connections are formed through the through electrodes, advantages are provided in that it is possible to achieve a high operation speed and miniaturization.
However, because the semiconductor chips are stacked in the state in which they are grinded thin through the back-grinding process, warping is likely to occur in the semiconductor chips so that stacking is difficult to conduct, and a crack is likely to occur in the semiconductor chips so that the manufacturing yield of the stacked semiconductor package decreases.